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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MCF53017 Rev. 3, 8/2009
MCF53017
LQFP-208 28 x 28 MAPBGA-256 17 x 17
MCF5301x Data Sheet
Features * Version 3 ColdFire(R) core with EMAC * Up to 211 Dhrystone 2.1 MIPS @ 240 MHz * 16 KBytes unified instruction/data cache * 128 KBytes internal SRAM with standby power supply support * Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters * Enhanced Secure Digital Host Controller (eSDHC) - Supports CE-ATA, SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMC plus, MMC 4x, and MMC RS cards * Two ISO7816 smart card interfaces * IC identification module * Voice-band audio codec with integrated speaker, microphone, headphone, and handset amplifiers * 16- or 32-bit SDR, 16-bit DDR/mobile-DDR SDRAM controller * USB 2.0 On-the-Go controller * USB host controller * 2 10/100 Ethernet MACs * Coprocessor for acceleration of the DES, 3DES, AES, MD5, and SHA-1 algorithms * Random number generator * 16-channel DMA controller * Synchronous serial interface * 4 periodic interrupt timers * 4 32-bit timers with DMA support * Real-time clock (RTC) module with standby support * DMA-supported serial peripheral interface (DSPI) * 3 UARTs * I2C bus interface
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2009. All rights reserved. Preliminary--Subject to Change Without Notice
Table of Contents
1 2 3 MCF5301x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6 3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .7 3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .7 3.4 Power Consumption Specifications. . . . . . . . . . . . . . . . .8 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9 4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2 Pinout--208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3 Pinout-256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . .18 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .19 5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .20 5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .21 5.4.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . .22 5.4.2 USB Power Filtering. . . . . . . . . . . . . . . . . . . . . .22 5.4.3 Supply Voltage Sequencing and Separation Cautions . . . . . . . . . . . . . . . . . . . . .23 5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .24 5.6 External Interface Timing Characteristics . . . . . . . . . . .25 5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .27 5.7.2 DDR SDRAM AC Timing Characteristics . . . . .30 5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .32 5.9 Reset and Configuration Override Timing. . . . . . . . . . .33 5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 5.12 I2C Input/Output Timing Specifications . . . . . . . . . . . . 5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 5.13.1 Receive Signal Timing Specifications . . . . . . . 5.13.2 Transmit Signal Timing Specifications . . . . . . . 5.13.3 Asynchronous Input Signal Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13.4 MII Serial Management Timing Specifications . 5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 5.16 eSDHC Electrical Specifications . . . . . . . . . . . . . . . . . 5.16.1 eSDHC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.2 eSDHC Electrical DC Characterisics . . . . . . . . 5.17 SIM Electrical Specifications . . . . . . . . . . . . . . . . . . . . 5.17.1 General Timing Requirements . . . . . . . . . . . . . 5.17.2 Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . 5.17.3 Power Down Sequence . . . . . . . . . . . . . . . . . . 5.18 IIM/Fusebox Electrical Specifications . . . . . . . . . . . . . 5.19 Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19.1 Voice Codec ADC Specifications . . . . . . . . . . . 5.19.2 Voice Codec DAC Specifications . . . . . . . . . . . 5.20 Integrated Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20.1 Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . 5.20.2 Handset Amplifier . . . . . . . . . . . . . . . . . . . . . . . 5.20.3 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . 5.20.4 Microphone Amplifier . . . . . . . . . . . . . . . . . . . . 5.21 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 5.22 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 37 37 37 38 38 39 39 41 41 42 43 43 44 45 46 46 47 51 55 55 56 57 57 58 60 61 61 62
4
5
6 7 8
MCF5301x Data Sheet, Rev. 3 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF53017
Version 3 ColdFire Core 16K Instruction/ Data Cache
JTAG
Oscillator
PLL
EMAC
BDM
2 FECs
USB Host
128K SRAM
Hardware Divide
CAU
eDMA
eSDHC
USB OTG
Crossbar Switch (XBS)
Splitter Peripheral Bridge Codec IIM Smart Card Interface I2C RTC & Oscillator 4 DMA Timers DSPI FlexBus GPIO SDRAM Controller
SSI
RNG
2 INTCs
2 EPORTs
3 UARTs
4 PITs
LEGEND
BDM CAU DSPI eDMA eSDHC EMAC EPORT FEC GPIO I2 C - Background debug module - Cryptography acceleration unit - DMA serial peripheral interface - Enhanced direct memory access module - Enhanced Secure Digital host controller - Enchanced multiply-accumulate unit - Edge port module - Fast Ethernet Controller - General purpose input/output module - Inter-Integrated Circuit IIM INTC JTAG PCI PIT PLL RNG RTC SSI USB OTG - IC identification module - Interrupt controller - Joint Test Action Group interface - Peripheral Component Interconnect - Programmable interrupt timers - Phase locked loop module - Random number generator - Real time clock - Synchronous serial interface - Universal Serial Bus On-the-Go controller
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
MCF5301x Family Comparison
1
MCF5301x Family Comparison
Table 1. MCF5301x Family Configurations
MCF53010 MCF53011 MCF53012 MCF53013 MCF53014 MCF53015 MCF53016 MCF53017 * * * * * * * * * * * * 2 3 * * * 4 * 4 * 2
The following table compares the various device derivatives available within the MCF5301x family.
Module
Version 3 ColdFire Core with EMAC (enhanced multiply-accumulate unit) Core (system) clock Peripheral and external bus clock (Core clock / 3) Performance (Dhrystone/2.1 MIPS) Unified data/instruction cache Static RAM (SRAM) Voice-over-IP software Cryptography acceleration unit (CAU) Random number generator Smart card interface (SIM) Voice-band audio codec Integrated audio amplifiers IC identification module (IIM) Enhanced Secure Digital host controller (eSDHC) SDR/DDR SDRAM controller FlexBus external interface USB 2.0 On-the-Go USB 2.0 Host Synchronous serial interface (SSI) Fast Ethernet controller (FEC) UARTs I
2C
*
*
*
*
*
*
*
up to 240 MHz up to 80 MHz up to 211 16 Kbytes 128 Kbytes -- -- -- -- * * 1 port * -- * -- * -- * -- 2 Kbits * * * * -- * 2 3 * * * 4 * 4 * 2 * * * * -- * 2 3 * * * 4 * 4 * 2 * * * * -- * 2 3 * * * 4 * 4 * 2 * * * * -- * 2 3 * * * 4 * 4 * 2 * * * * * * 2 3 * * * 4 * 4 * 2 * * * * * * 2 3 * * * 4 * 4 * 2 * * * * * * 2 3 * * * 4 * 4 * 2 * * * * * -- -- * * * -- -- -- -- * * * -- -- 2 ports * *
DSPI Real-time clock 32-bit DMA timers Watchdog timer (WDT) Periodic interrupt timers (PIT) Edge port module (EPORT) Interrupt controllers (INTC)
MCF5301x Data Sheet, Rev. 3 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Ordering Information
Table 1. MCF5301x Family Configurations (continued)
MCF53010 MCF53011 MCF53012 MCF53013 MCF53014 MCF53015 MCF53016 MCF53017 * * * 5
Module
16-channel direct memory access (DMA) General purpose I/O Module (GPIO) JTAG - IEEE(R) 1149.1 Test Access Port Package
* * *
* * *
* * *
* * *
* * *
* * *
* * *
208 LQFP
256 MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number MCF53010CQT240 MCF53011CQT240 MCF53012CQT240 MCF53013CQT240 MCF53014CMJ240J MCF53015CMJ240J MCF53016CMJ240J MCF53017CMJ240J Description MCF53010 Microprocessor MCF53011 Microprocessor 208 LQFP MCF53012 Microprocessor MCF53013 Microprocessor 240 MHz MCF53014 Microprocessor MCF53015 Microprocessor 256 MAPBGA MCF53016 Microprocessor MCF53017 Microprocessor -40 to +85 C Package Speed Temperature
3
3.1
Hardware Design Considerations
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 1 should be connected between the board IVDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PVDD pin as possible. The 10-ohm resistor in the given filter is required, do not implement the filter circuit using only capacitors. The PVDD pins draw very little current, so concerns regarding voltage loss across the 10-ohm resistor are not valid.
10 Board IVDD 10 F 0.1 F PLL VDD Pin
GND
Figure 1. System PLL VDD Power Filter
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Hardware Design Considerations
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 2 should be connected between the board EVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible.
Board EVDD 0 10 F 0.1 F USB VDD Pin
GND
Figure 2. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown.
3.3
Supply Voltage Sequencing
Figure 3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal logic / core VDD (IVDD). The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V or 1.8V) and EVDD are specified relative to IVDD.
3.3V
Supplies Stable
EVDD, USBVDD (3.3V)
DC Power Supply Voltage
2.5V 1.8V 1.2V 1
SDVDD (2.5V - DDR) SDVDD (1.8V - DDR) IVDD, PVDD
2
0 Time
Notes:
1 2
IVDD should not exceed EVDD, SDVDD or PVDD by more than 0.4V at any time, including power-up. Recommended that IVDD/PVDD should track EVDD/SDVDD up to 0.9V then separate for completion of ramps 3 Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PVDD) by more than 0.5V at any time, including during power-up. 4 Use 1 microsecond or slower rise time for all supplies.
Figure 3. Supply Voltage Sequencing and Separation Cautions
MCF5301x Data Sheet, Rev. 3 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Hardware Design Considerations
3.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must power up. IVDD should not lead the EVDD, SDVDD or PVDD by more than 0.4V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. 2. Use 1 microsecond or slower rise time for all supplies. IVDD/PVDD and EVDD/SDVDD should track up to 0.9V and then separate for the completion of ramps with EVDD/SDVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
3.3.2
Power Down Sequence
If IVDD/PVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PVDD going low by more than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. Drop IVDD/PVDD to 0V. Drop EVDD/SDVDD supplies.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Hardware Design Considerations
3.4
Power Consumption Specifications
Estimated maximum RUN mode power consumption measurements are shown in the below figure.
Estimated Power Consumption vs. Core Frequency 300 250 200 150 100 50 0 0 40 80 120 160 200 240 Core Frequency (MHz)
Figure 4. Estimated Maximum RUN Mode Power Consumption Table 3 lists estimated maximum power and current consumption for the device in various operating modes. Table 3. Estimated Maximum Power Consumption Specifications
Characteristic Run Mode -- Total Power Dissipation Static Dynamic Core Operating Supply Current 1 Run Mode Pad Operating Supply Current Run Mode (application dependent) Wait Mode Stop Mode
1
Power Consumption (mW)
Symbol
Typical -- -- --
Max TBD TBD TBD 82.9 TBD TBD TBD
Unit mW mW mW mA mA mA mA
IDD -- EIDD -- -- --
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
MCF5301x Data Sheet, Rev. 3 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 4. Current Measurementas at Different VCO vs. Core Frequencies
Stop Mode Executing Run Wait Doze Stop(0) Stop(1) Stop(2) Stop(3) 480VCO, 240MHz core 55.3mA 39.5mA 16.28mA 16.19mA 8.41mA 8.13mA 1.83mA 0.65mA 240VCO, 120MHz core 28.36mA 20.3mA 8.53mA 8.53mA 4.60mA 4.48mA 1.86mA 0.66mA 480VCO, 120MHz core 30.00mA 22.02mA 10.23mA 10.18mA 6.29mA 6.15mA 1.87mA 0.67mA 480VCO, 48MHz core 13.6mA 10.29mA 5.53mA 5.55mA 3.90mA 3.88mA 1.82mA 0.67mA Limp Mode, 20HMHz crystal 5.90mA 4.42mA 2.43mA 2.41mA 1.78mA 1.77mA 1.76mA 0.65mA
4
4.1
Pin Assignments and Reset States
Signal Multiplexing
The following table lists all the MCF5301x pins grouped by function. The "Dir" column is the direction for the primary function of the pin only. Refer to Section 4.2, "Pinout--208 LQFP," and Section 4.3, "Pinout-256 MAPBGA," for package diagrams. For a more detailed discussion of the MCF3xxx signals, consult the MCF5301x Reference Manual (MCF53017RM).
NOTE
In this table and throughout this document a single signal within a group is designated without square brackets (i.e., FB_A23), while designations for multiple signals within a group use brackets (i.e., FB_A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that are muxed with GPIO will default to their GPIO functionality. See Table 5 for a list of the exceptions. Table 5. Special-Case Default Signal Functionality
Pin FB_BE/BWE[3:0] FB_CS[3:0] FB_OE FB_TA FB_R/W FB_TS Default Signal FB_BE/BWE[3:0] FB_CS[3:0] FB_OE FB_TA FB_R/W FB_TS
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2 MCF53010 MCF53011 MCF53012 MCF53013 208 LQFP MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
Reset RESET RSTOUT -- -- -- -- -- -- Clock EXTAL XTAL -- -- -- -- -- -- Mode Selection BOOTMOD[1:0] -- -- -- FlexBus FB_A[23:22] FB_A[21:16] FB_A[15:14] FB_A[13:11] FB_A10 FB_A[9:0] FB_D[31:16] -- -- -- -- -- -- -- FB_CS[3:2] -- SD_BA[1:0] SD_A[13:11] -- SD_A[9:0] SD_D[31:16] -- -- -- -- -- -- -- -- -- -- -- -- -- --
O O O O O O I/O SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD 115, 114 113-108 107, 106 105-103 100 99-97 95-89 208-198, 57-62, 64, 65 P16, N16 R16, N14, N15, P15-13 R15, R14 N13, R12, R13 N12 P12, T14, T15, R11, P11, N11, T13, R10, T11, T12 B3, A2, D6, C5, B4, A3, B5, C6, D12, C14, B14, C13, D11, B13, A14, A13 B9, A9, A8, D7, B8, C8, D8, B7, C10, A10, B10, D10, C11, A11, B11, A12 D13 A4, B12, C9, D9 B6, C7 D2 C2 D4 B2 C3 D3
U --
I O
EVDD EVDD
41 42
M3 N1
-- U3
I O
EVDD EVDD
49 50
T2 T3
--
I
EVDD
55, 17
J5, G5
FB_D[15:0]
--
FB_D[31:16]
--
--
I/O
SDVDD 182-189, 177-170
FB_CLK FB_BE/BWE[3:0] FB_CS[5:4] FB_CS1 FB_CS0 FB_OE FB_TA FB_R/W FB_TS
-- PBE[3:0] PCS[5:4] PCS1 PCS0 PFBCTL3 PFBCTL2 PFBCTL1 PFBCTL0
-- SD_DQM[3:0] -- SD_CS1 FB_CS4 -- -- -- DACK0
-- -- -- -- -- -- -- -- -- SDRAM Controller
-- -- -- -- -- -- U -- --
O O O O O O I O O
SDVDD
153
SDVDD 197, 166, 179, 178 SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD -- 5 6 1 3 2 4
SD_A10
--
--
--
--
O
SDVDD
206
C4
MCF5301x Data Sheet, Rev. 3 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2 MCF53010 MCF53011 MCF53012 MCF53013 208 LQFP
154 151 190 191 155 196, 167 152 207 150
Signal Name
GPIO
Alternate 1
Alternate 2
MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA
D15 B15 A7 A6 A15 C12, A5 C15 D5 D14
SD_CAS SD_CKE SD_CLK SD_CLK SD_CS0 SD_DQS[1:0] SD_RAS SD_SDR_DQS SD_WE
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- External Interrupts Port 14,5
-- -- -- -- -- -- -- -- --
O O O O O O O I O
SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD
IRQ1DEBUG[7:4] IRQ1DEBUG[3:0] IRQ1FEC7 IRQ1FEC6 IRQ1FEC5 IRQ1FEC4 IRQ1FEC[3:2] IRQ1FEC[1:0]
PIRQ1DEBUG [7:4] PIRQ1DEBUG [3:0] PIRQ1FEC7 PIRQ1FEC6 PIRQ1FEC5 PIRQ1FEC4 PIRQ1FEC[3:2] PIRQ1FEC[1:0]
DDATA[3:0] PST[3:0] RMII1_CRS_DV RMII1_RXER RMII1_TXEN RMII1_REF_CLK RMII1_RXD[1:0] RMII1_TXD[1:0]
-- -- MII0_CRS MII0_RXCLK MII0_TXCLK -- MII0_RXD[3:2] MII0_TXD[3:2]
-- -- -- -- -- D -- --
I
EVDD
--
H1, H4-2
I
EVDD
--
K14, H14, K15, J13
I I I I I I
EVDD EVDD EVDD EVDD EVDD EVDD
29 30 31 32 33, 34 35, 36
J1 J2 K4 J3 J4, K1 K2, L1
External Interrupts Port 05 IRQ07 IRQ06 IRQ04 IRQ01 PIRQ07 PIRQ06 PIRQ04 PIRQ01 -- -- DREQ0 DREQ1 -- USB_CLKIN -- -- U U U U
I I I I EVDD EVDD EVDD EVDD 10 -- 19 11 E4 L13 D1 F4
Enhanced Secure Digital Host Controller SDHC_DAT3 SDHC_DAT[2:0] SDHC_CMD SDHC_CLK PSDHC5 PSDHC[4:2] PSDHC1 PSDHC0 -- -- -- -- -- -- -- -- UD U U --
I/O I/O I/O O EVDD EVDD EVDD EVDD 60 61-63 59 58 N4 R5, N6, N5 R4 R3
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2 MCF53010 MCF53011 MCF53012 MCF53013 208 LQFP MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
Codec CODEC_ADCN CODEC_ADCP CODEC_BGRVREF CODEC_DACN CODEC_DACP CODEC_REGBYP CODEC_REFN CODEC_REFP CODEC_VAG -- -- -- -- -- -- -- -- -- AMP_MICN AMP_MICP -- AMP_HSN AMP_HSP -- -- -- -- -- -- -- -- -- -- -- -- -- Amplifiers AMP_HPDUMMY AMP_HPOUT AMP_SPKRN AMP_SPKRP -- -- -- -- -- -- -- -- -- -- -- -- Smart Card interface 1 SIM1_DATA SIM1_VEN SIM1_RST SIM1_PD SIM1_CLK PSIM14 PSIM13 PSIM12 PSIM11 PSIM10 SSI_TXD SSI_RXD SSI_FS SSI_BCLK SSI_MCLK U1TXD U1RXD U1RTS U1CTS -- Smart Card interface 0 SIM0_DATA SIM0_VEN SIM0_RST SIM0_PD SIM0_CLK PSIM04 PSIM03 PSIM02 PSIM01 PSIM00 -- -- -- -- -- -- -- -- -- -- USB On-the-Go USBO_DM USBO_DP -- -- -- -- -- -- -- --
O O USB VDD USB VDD 148 149 C16 B16
-- -- -- -- -- -- -- -- --
I I I O O I I I I
85 84 86 75 67 81 79 78 82
P10 P9 N9 R7 R6 P6 P8 P7 N7
-- -- -- --
O O O O
-- -- -- --
R9 R8 T9 T7
UD UD -- -- --
I/O O O O O
EVDD EVDD EVDD EVDD EVDD
141 142 144 145 143
E14 D16 E13 E15 F13
-- -- -- -- --
I/O O O O O
EVDD EVDD EVDD EVDD EVDD
-- -- -- -- --
L3 M2 F16 L14 M16
MCF5301x Data Sheet, Rev. 3 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2 MCF53010 MCF53011 MCF53012 MCF53013 208 LQFP MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
USB Host USBH_DM USBH_DP -- -- -- -- -- -- FEC 1 RMII1_MDC RMII1_MDIO PFECI2C5 PFECI2C4 -- -- MII0_TXER MII0_COL FEC 0 RMII0_CRS_DV RMII0_RXD[1:0] RMII0_RXER RMII0_TXD[1:0] RMII0_TXEN RMII0_MDC RMII0_MDIO PFEC06 PFEC0[5:4] PFEC03 PFEC0[2:1] PFEC00 PFECI2C3 PFECI2C2 -- -- -- -- -- -- -- MII0_RXDV MII0_RXD[1:0] MII0_RXER MII0_TXD[1:0] MII0_TXEN MII0_MDC MII0_MDIO Real Time Clock RTC_EXTAL RTC_XTAL -- -- -- -- -- -- -- --
I O EVDD EVDD -- -- P1 R1
-- --
O O
USB VDD USB VDD
-- --
B1 C1
-- --
EVDD EVDD
22 23
E1 F1
-- -- -- -- D -- --
EVDD EVDD EVDD EVDD EVDD EVDD EVDD
131 130, 129 127 125, 124 123 133 132
G16 H15, H16 J16 J15, J14 K16 G14 G15
Synchronous Serial Interface SSI_RXD SSI_TXD SSI_FS SSI_MCLK SSI_BCLK PSSI4 PSSI3 PSSI2 PSSI1 PSSI0 -- -- -- -- -- U1RXD U1TXD U1RTS SSI_CLKIN U1CTS I2C I2C_SCL I2C_SDA PFECI2C1 PFECI2C0 U2RXD U2TXD RMII1_MDC RMII1_MDIO DSPI DSPI_PCS3 DSPI_PCS2 PDSPI6 PDSPI5 USBH_VBUS_EN USBH_VBUS_OC -- -- -- --
I/O I/O EVDD EVDD -- -- P2 N2
UD UD -- -- --
I O I/O O I/O
EVDD EVDD EVDD EVDD EVDD
-- -- -- -- --
N3 P3 R2 P4 P5
U U
I/O I/O
EVDD EVDD
37 38
M1 K3
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2 MCF53010 MCF53011 MCF53012 MCF53013 208 LQFP
140 137 134 136 135
Signal Name
GPIO
Alternate 1
Alternate 2
MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA
F14 G13 H13 E16 F15
DSPI_PCS1 DSPI_PCS0/SS DSPI_SCK DSPI_SIN DSPI_SOUT
PDSPI4 PDSPI3 PDSPI2 PDSPI1 PDSPI0
-- U2RTS U2CTS U2RXD U2TXD
-- -- -- -- -- UARTs
-- U -- -- --
I/O I/O I/O I O
EVDD EVDD EVDD EVDD EVDD
U2RXD U2TXD U0CTS U0RTS U0RXD U0TXD
PUART5 PUART4 PUART3 PUART2 PUART1 PUART0
-- -- USBO_VBUS_EN USBO_VBUS_OC -- --
-- -- USB_PULLUP -- -- -- DMA Timers
-- -- -- -- -- --
I O I O I O
EVDD EVDD EVDD EVDD EVDD EVDD
14 18 20 21 27 28
E2 F2 G4 G3 G2 G1
T3IN T2IN T1IN T0IN
PTIMER3 PTIMER2 PTIMER1 PTIMER0
T3OUT T2OUT T1OUT T0OUT
IRQ03 IRQ02 DACK1 CODEC_ALTCLK BDM/JTAG6
-- -- -- --
I I I I
EVDD EVDD EVDD EVDD
13 12 122 121
F3 E3 K13 L16
ALLPST JTAG_EN PSTCLK DSI DSO BKPT DSCLK
PDEBUG -- -- -- -- -- --
-- -- TCLK TDI TDO TMS TRST
-- -- -- -- -- -- --
-- D -- U -- U U
O I I I O I I
EVDD EVDD EVDD EVDD EVDD EVDD EVDD
43 64 65 66 120 119 118
-- M8 T5 T4 M15 M14 L15
MCF5301x Data Sheet, Rev. 3 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2 MCF53010 MCF53011 MCF53012 MCF53013 208 LQFP MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
Test TEST -- -- -- Power Supplies IVDD EVDD -- -- -- -- -- -- -- -- -- -- -- --
16, 44, 69, 77, 128, E9, F8, F9, H5, H6, H11, 169, 193 H12, J6, J11, L8, L9 9, 24, 26, 40, 47, F5, G6, G11, G12, 51, 54, 57, 74, 126, J12, K6, K11, K12, 139, 195 L5-7, L10-12, M5-7, M12 7, 102, 116, 156, 163, 181, 208 46 147 -- -- 80 -- 96 -- -- 8, 15, 25, 39, 45, 48, 52, 53, 56, 68, 73, 76, 101, 117, 138, 168, 180, 192, 194 83 -- -- N8 T8 M9 L2 L4 A1, A16, G7-10, H7-10, J7-10, K7-10, T1, T16 E5, E6, E10-12, F6, F7, F10, F11 M4 E7 E8
D
I
EVDD
146
F12
SD_VDD VDD_OSC_A_PLL VDD_USBO VDD_USBH VDD_RTC AVDD_CODEC AVDD_SPKR VDD_EPM VSTBY_SRAM VSTBY_RTC VSS
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
VSS_CODEC AVSS_SPKR_HDST AVSS_SPKR_HP
1 2 3 4 5 6
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
N10 T6 T10
Pull-ups are generally only enabled on pins with their primary function, except as noted. Refers to pin's primary function. Enabled only in oscillator bypass mode (internal crystal oscillator is disabled). The edge port 1 signals are the primary functions on two sets of pins (IRQ1FECn and IRQ1DEBUGn). If an IRQ1 function is configured on both pins, the IRQ1FECn pin takes priority. The corresponding IRQ1DEBUGn pin is disconnected internally from the edge port 1 module. GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
Pin Assignments and Reset States
4.2
Pinout--208 LQFP
FB_BE/BWE3
The pinout for the 208 LQFP devices is shown in Figure 5 and Figure 6.
SDVDD SDR_DQS SD_A10 FB_D31 FB_D30 FB_D29 FB_D28 FB_D27 FB_D26 FB_D25 FB_D24 SD_DQS1 EVDD VSS IVDD VSS SD_CLK SD_CLK FB_D8 FB_D9 FB_D10 FB_D11 FB_D12 FB_D13 FB_D14
FB_OE FB_R/W FB_TA FB_TS FB_CS1 FB_CS0 SDVDD VSS EVDD IRQ07 IRQ01 T2IN T3IN U2RXD VSS IVDD BOOTMOD0 U2TXD IRQ04 U0CTS U0RTS RMII1_MDC RMII1_MDIO EVDD VSS EVDD U0RXD U0TXD IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 I2C_SCL I2C_SDA VSS EVDD RESET RSTOUT ALLPST IVDD VSS VDD_OSC EVDD VSS EXTAL XTAL EVDD
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VSS EVDD BOOTMOD1 VSS EVDD SDHC_CLK SDHC_CMD SDHC_DAT3 SDHC_DAT2 SDHC_DAT1 SDHC_DAT0 JTAG_EN TCLK TDI CODEC_DACP VSS IVDD
Figure 5. MCF53010, MCF53011, MCF53012, and MCF53013 Pinout Top View, Left (208 QFP)
MCF5301x Data Sheet, Rev. 3 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
VSS EVDD CODEC_DACN VSS IVDD CODEC_REFP
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183
*
Pin Assignments and Reset States
FB_D15 SDVDD VSS FB_BE/BWE1 FB_BE/BWE0 FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 FB_D2 FB_D1 FB_D0 IVDD VSS SD_DQS0 FB_BE/BWE2 FB_D16 FB_D17 SDVDD FB_D18 FB_D19 FB_D20 FB_D21 FB_D22 FB_D23 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
SDVDD SD_CS0 SD_CAS FB_CLK SD_RAS SD_CKE SD_WE USBO_DP USBO_DM VDD_USBO TEST SIM1_PD SIM1_RST SIM1_CLK SIM1_VEN SIM1_DATA DSPI_PCS1 EVDD VSS DSPI_PCS0 DSPI_SIN DSPI_SOUT DSPI_SCK RMII0_MDC RMII0_MDIO RMII0_CRSDV RMII0_RXD1 RMII0_RXD0 IVDD RMII0_RXER EVDD RMII0_TXD1 RMII0_TXD0 RMII0_TXEN T1IN T0IN TDO TMS TRST VSS SDVDD FB_A23 FB_A22 FB_A21 FB_A20 FB_A19 FB_A18 FB_A17 FB_A16 FB_A15 FB_A14 FB_A13
Freescale Semiconductor
CODEC_REFN AVDD_CODEC CODEC_REGBYP CODEC_VAG VSS_CODEC CODEC_ADCP CODEC_ADCN CODEC_BGRVREF CODEC_ATSTP CODEC_ATSTN FB_A0 FB_A1 FB_A2 FB_A3 FB_A4 FB_A5 FB_A6 AVDD_EPM FB_A7 FB_A8 FB_A9 FB_A10 VSS SDVDD FB_A11 FB_A12
Figure 6. MCF53010, MCF53011, MCF53012, and MCF53013 Pinout Top View, Right (208 QFP)
MCF5301x Data Sheet, Rev. 3 Preliminary--Subject to Change Without Notice 17
Pin Assignments and Reset States
4.3
1
Pinout-256 MAPBGA
2 FB_D 30 3 FB_D 26 4 FB_BE/ BWE3 5 SD_ DQS1 6 SD_ CLK 7 SD_ CLK 8 FB_D 13 9 FB_D 14 10 FB_D 6 11 FB_D 2 12 FB_D 0 13 FB_D 16 14 FB_D 17 15 16
The pinout for the MCF53014, MCF53015, MCF53016, and MCF53017 packages are shown below.
A
VSS
SD_CS
VSS
A
B
USBH_ DM
FB_TA
FB_D 31
FB_D 27
FB_D 25
FB_CS5
FB_D 8
FB_D 11
FB_D 15
FB_D 5
FB_D 1
FB_BE/ BWE2
FB_D 18
FB_D 21
SD_ CKE
USBO_ B DP
C
USBH_ DP
FB_CS0 FB_R/W SD_A10
FB_D 28
FB_D 24
FB_CS4
FB_D 10
FB_BE/ BWE1
FB_D 7
FB_D 3
SD_ DQS2
FB_D 20
FB_D 22
SD_ RAS
USBO_ C DM
D
IRQ04
FB_CS1
FB_TS
FB_OE
SD_SDR _DQS
FB_D 29
FB_D 12
FB_D 9
FB_BE/ BWE0
FB_D 4
FB_D 19
FB_D 23
FB_CLK
SD_ WE
SD_ CAS
SIM1_ VEN
D
E
RMII1_ MDC
U2RXD
T2IN
IRQ07
SDVDD
SDVDD
VDD_ USBO
VDD_ USBH
IVDD
SDVDD
SDVDD
SDVDD
SIM1_ RST
SIM1_ DATA
SIM1_ PD
DSPI_ SIN
E
F
RMII1_ MDIO
U2TXD
T3IN
IRQ01
EVDD
SDVDD
SDVDD
IVDD
IVDD
SDVDD
SDVDD
TEST
SIM1_ CLK
DSPI_ PCS1
DSPI_ SOUT
SIM0_ RST
F
G
U0TXD
U0RXD
U0RTS
U0CTS
BOOT MOD0
EVDD
VSS
VSS
VSS
VSS
EVDD
EVDD
DSPI_ PCS0
RMII0_ MDC
RMII0_ MDIO
RMII0_ G CRSDV
H
IRQ1 IRQ1 IRQ1 IRQ1 DEBUG7 DEBUG4 DEBUG5 DEBUG6
IVDD
IVDD
VSS
VSS
VSS
VSS
IVDD
IVDD
DSPI_ SCK
IRQ1 DEBUG2
RMII0_ RXD1
RMII0_ H RXD0
J
IRQ1 FEC7
IRQ1 FEC6
IRQ1 FEC4
IRQ1 FEC3
BOOT MOD1
IVDD
VSS
VSS
VSS
VSS
IVDD
EVDD
IRQ1 DEBUG0
RMII0_ TXD0
RMII0_ TXD1
RMII0_ RXER
J
K
IRQ1 FEC2
IRQ1 FEC1
I2C_ SDA
IRQ1 FEC5
NC
EVDD
VSS
VSS
VSS
VSS
EVDD
EVDD
T1IN
IRQ1 IRQ1 RMII0_ K DEBUG3 DEBUG1 TXEN
L
IRQ1 FEC0
VSTBY_ SRAM
SIM0_ DATA
VSTBY_ RTC VDD_ OSC_A_ PLL SDHC_ DAT3
EVDD
EVDD
EVDD
IVDD
IVDD
EVDD
EVDD
EVDD
IRQ06
SIM0_ PD
TRST
T0IN
L
M
I2C_ SCL
SIM0_ VEN
RESET
EVDD
EVDD
EVDD
JTAG_ EN
VDD_ EPM
NC
NC
EVDD
NC
TMS
TDO
SIM0_ CLK
M
N
RST OUT
DSPI_ PCS2
SSI_ RXD
SDHC_ DAT0
SDHC_ CODEC AVDD_ DAT1 _VAG CODEC
CODEC VSS_ _BGR CODEC VREF
FB_A4
FB_A10 FB_A13
FB_A20
FB_A19 FB_A22 N
P
RTC_ EXTAL
DSPI_ PCS3
SSI_ TXD
SSI_ MCLK
SSI_ BCLK
CODEC CODEC CODEC CODEC CODEC _REG _REFP _REFN _ADCP _ADCN BYP CODEC CODEC _DACP _DACN AVSS_ SPKR_ HDST 6 AMP_ HP OUT AVDD_ SPKR 8 AMP_ HP DUMMY AMP_ SPKRN 9
FB_A5
FB_A9
FB_A16
FB_A17
FB_A18 FB_A23 P
R
RTC_ XTAL
SSI_FS
SDHC_ CLK
SDHC_ CMD
SDHC_ DAT2
FB_A2
FB_A6
FB_A12 FB_A11
FB_A14
FB_A15 FB_A21 R
T VSS EXTAL XTAL TDI TCLK
AMP_ SPKRP 7
AVSS_ SPKR_ HP 10
FB_A1
FB_A0
FB_A3
FB_A8
FB_A7
VSS
T
1
2
3
4
5
11
12
13
14
15
16
Figure 7. MCF53014, MCF53015, MCF53016, and MCF53017 Pinout (256 MAPBGA)
MCF5301x Data Sheet, Rev. 3 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
5
Preliminary Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5301x microprocessor. This section contains detailed information on DC/AC electrical characteristics and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module specifications.
5.1
Maximum Ratings
Table 7. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage CMOS Pad Supply Voltage DDR/Memory Pad Supply Voltage PLL Supply Voltage Digital Input Voltage
3
Symbol IVDD EVDD SDVDD PLLVDD VIN ID TA (TL - TH) Tstg
Value -0.5 to +2.0 -0.3 to +4.0 -0.3 to +4.0 -0.3 to +2.0 -0.3 to +3.6 25 -40 to +85 -55 to +150
Unit V V V V V mA C C
Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range
1
2
3
4 5
Functional operating conditions are given in Section 5.4, "DC Electrical Specifications." Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or EVDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and EVDD. Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Insure external EVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Preliminary Electrical Characteristics
5.2
Thermal Characteristics
Table 8. Thermal Characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
Symbol Four layer board (2s2p) Four layer board (2s2p) JMA JMA JB JC jt Tj
256MBGA 361,2 321,2 253 14 2
4
208LQFP TBD TBD TBD TBD TBD TBD
Unit C/W C/W C/W C/W C/W
o
1,5
105
C
2 3 4 5
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA )
Eqn. 1
Where:
TA QJMA PD PINT PI/O = = = = = Ambient Temperature, C Package Thermal Resistance, Junction-to-Ambient, C/W PINT + PI/O IDD x IVDD, Watts - Chip Internal Power Power Dissipation on Input and Output Pins -- User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K P D = -------------------------------( T J + 273C )
Eqn. 2
Solving equations 1 and 2 for K gives: K = P D x ( T A x 273C ) + Q JMA x P D
2
Eqn. 3
MCF5301x Data Sheet, Rev. 3 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
5.3
ESD Protection
Table 9. ESD Protection Characteristics1, 2
Characteristics ESD Target for Human Body Model
1 2
Symbol HBM
Value 2000
Units V
All ESD testing is in conformity with JEDEC JESD22-A114 specification. A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 10. DC Electrical Specifications
Characteristic Symbol IVDD SRAMVSTBY RTCVSTBY PLLVDD EVDD SDVDD 1.70 2.25 3.0 USBVDD EVIH EVIL EVOH EVOL SDVIH 3.0 0.51 x EVDD VSS - 0.3 0.8 x EVDD -- 1.95 2.75 3.6 3.6 EVDD + 0.3 0.42 x EVDD -- 0.2 x EVDD V V V V V V SDVDD x 0.7 Vref+0.15 2 -0.3 -0.3 VSS - 0.3 SDVDD+0.3 SDVDD+0.3 SDVDD + 0.3 V SDVDD x 0.3 Vref+0.15 0.8 Min 1.08 1.08 3.0 3.0 3.0 Max 1.32 1.32 3.6 3.6 3.6 Unit V V V V V V
Core Supply Voltage SRAM Standby Voltage RTC Standby Voltage PLL Supply Voltage CMOS Pad Supply Voltage SDRAM and FlexBus Supply Voltage Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) USB Supply Voltage CMOS Input High Voltage CMOS Input Low Voltage CMOS Output High Voltage IOH = -2.0 mA CMOS Output Low Voltage IOL = 2.0 mA SDRAM and FlexBus Input High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDRAM and FlexBus Input Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVIL
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Preliminary Electrical Characteristics
Table 10. DC Electrical Specifications (continued)
Characteristic SDRAM and FlexBus Output High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOH = -5.0 mA for all modes SDRAM and FlexBus Output Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOL = 5.0 mA for all modes Input Leakage Current Vin = VDD or VSS, Input-only pins Weak Internal Pull-Up/Pull-down Device Current1 Selectable Weak Internal Pull-Up/Pull-down Device Current2 Input Capacitance All input-only pins All input/output (three-state) pins
1 2 3
Symbol SDVOH
Min SDVDD x 0.9 SDVDD - 0.35 2.9
Max -- -- --
Unit V
SDVOL -- -- -- Iin IAPU IAPU Cin -- -- -2.5 10 25
V SDVDD x 0.1 0.35 0.4 2.5 315 150 7 7 A A A pF
Refer to the signals section for pins having weak internal pull-up devices. Refer to the signals section for pins having weak internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested.
5.4.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 8 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible.
10 Board IVDD 10 F 0.1 F PLL VDD Pin
GND
Figure 8. System PLL VDD Power Filter
5.4.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 2 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible.
MCF5301x Data Sheet, Rev. 3 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics 0 Board EVDD 10 F 0.1 F USB VDD Pin
GND
Figure 9. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown.
5.4.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
5.4.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on the internal ESD protection clamp diodes.
5.4.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. Drop IVDD/PLLVDD to 0 V. Drop EVDD/SDVDD supplies.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Preliminary Electrical Characteristics
5.5
Num 1
Oscillator and PLL Electrical Characteristics
Table 11. PLL Electrical Characteristics
Characteristic PLL Reference Frequency Range Crystal reference External reference Core frequency CLKOUT Frequency2 Crystal Start-up Time3, 4 EXTAL Input High Voltage Crystal Mode5 All other modes (External, Limp) EXTAL Input Low Voltage Crystal Mode5 All other modes (External, Limp) PLL Lock Time 3, 6 Duty Cycle of reference XTAL Current Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL Crystal capacitive load Discrete load capacitance for XTAL
3
Symbol
Min. Value 14 14 488 x 10-6 163 x 10-6 -- VXTAL + 0.4 EVDD/2 + 0.4 -- -- -- 40 1 -- -- -- --
Max. Value 251 481 240 80 10 -- -- VXTAL - 0.4 EVDD/2 - 0.4 750 60 3 1.5 1.5 See crystal spec 2 x CL - CS_XTAL - CPCB_XTAL7 2 x CL - CS_EXTAL - CPCB_EXTAL7 TBD TBD 2.2 667
Unit
fref_crystal fref_ext fsys fsys/3 tcst VIHEXT VIHEXT VILEXT VILEXT tlpll tdc IXTAL CS_XTAL CS_EXTAL CL CL_XTAL
MHz MHz MHz MHz ms V V V V us % mA pF pF
2 3 4
5
7 8 9 10 11 12 13
pF
14
Discrete load capacitance for EXTAL
CL_EXTAL
--
pF
17
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter Frequency Modulation Range Limit 3, 10, 11 (fsysMax must not be exceeded) VCO Frequency. fvco = (fref x PFD)/4
Cjitter -- -- Cmod fvco 0.8 200 % fsys/3 % fsys/3 %fsys/3 MHz
18 19
1 2 3 4 5 6 7
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency. All internal registers retain data at 0 Hz. This parameter is guaranteed by characterization before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This parameter is guaranteed by design rather than 100% tested. This specification is the PLL lock time only and does not include oscillator start-up time.. CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
MCF5301x Data Sheet, Rev. 3 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. 10 Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100kHz. 11 Modulation range determined by hardware design.
5.6
External Interface Timing Characteristics
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. All other timing relationships can be derived from these values. Timings listed in Table 12 are shown in Figure 11 and Figure 12.
* The timings are also valid for inputs sampled on the negative clock edge. FB_CLK (80MHz)
TSETUP THOLD 1.5V
Table 12 lists processor bus input timings.
Input Setup And Hold
Invalid
1.5V
Valid
1.5V
Invalid
trise
Input Rise Time
Vh = VIH Vl = VIL
tfall
Input Fall Time
Vh = VIH Vl = VIL
FB_CLK
B4 B5
Inputs
Figure 10. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Preliminary Electrical Characteristics
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is 1`compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
Table 12. FlexBus AC Timing Specifications
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock.
Num Frequency of Operation FB1 FB2 FB3 FB4 FB5 FB6 FB7
1
Characteristic
Symbol
Min --
Max 80 -- 7.0 -- -- -- -- --
Unit Mhz ns ns ns ns ns ns ns
Notes fsys/3 tcyc
1
Clock Period (FB_CLK) Address, Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) Address, Data, and Control Output Hold (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) Data Input Setup Data Input Hold Transfer Acknowledge (TA) Input Setup Transfer Acknowledge (TA) Input Hold
tFBCK tFBCHDCV tFBCHDCI tDVFBCH tDIFBCH tCVFBCH tCIFBCH
12.5 -- 1 3.5 0 4 0
1, 2
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, "DDR SDRAM AC Timing Characteristics" for SD_CS[3:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the MCF5301x Reference Manual for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read and write bus cycles the address signals are indeterminate.
MCF5301x Data Sheet, Rev. 3 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[23:0] FB2 ADDR[31:X] DATA FB4 FB5
FB_A[23:0] FB_D[31:X]
FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn
FB6 FB7
FB_TA
Figure 11. FlexBus Read Timing
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[23:0] FB2
FB_A[23:0]
FB_D[31:X] FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA
ADDR[31:X]
DATA
FB6 FB7
Figure 12. Flexbus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device's SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Preliminary Electrical Characteristics
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS signal and its usage. Table 13. SDR Timing Specifications
Symbol Characteristic Frequency of operation SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12
1 2 3 4 5 6
Symbol
Min 50
Max 80 20 0.55 0.55 0.5 x SD_CLK + 1.0 -- Self timed 0.40 x SD_CLK
Unit Mhz ns SD_CLK SD_CLK ns ns ns ns
Notes
1 2 3 4
Clock period Pulse width high Pulse width low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] output valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] output hold SD_SDR_DQS output valid SD_DQS[3:0] input setup relative to SD_CLK SD_DQS[3:2] input hold relative to SD_CLK Data (D[31:0]) input setup relative to SD_CLK (reference only) Data input hold relative to SD_CLK (reference only) Data (D[31:0]) and data mask (SD_DQM[3:0]) output valid Data (D[31:0]) and data mask (SD_DQM[3:0]) output hold
tSDCK tSDCKH tSDCKH tSDCHACV tSDCHACI tDQSOV tDQVSDCH tDQISDCH tDVSDCH tDISDCH tSDCHDMV tSDCHDMI
12.5 0.45 0.45 -- 2.0 -- 0.25 x SD_CLK
5 6
Does not apply. 0.5xSD_CLK fixed width. 0.25 x SD_CLK 1.0 -- 1.5 -- -- 0.75 x SD_CLK + 0.5 -- ns ns ns ns
7
8
7 8
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock. Please see the PLL chapter of the MCF5301x Reference Manual for more information on setting the SDRAM clock rate. SD_CLK is one SDRAM clock in (ns). Pulse width high plus pulse width low cannot exceed min and max clock period. Pulse width high plus pulse width low cannot exceed min and max clock period. SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat. SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat. The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is just provided as guidance.
MCF5301x Data Sheet, Rev. 3 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
SD1 SD_CLK
SD2
SD3 SD5 SD_CSn SD_RAS SD_CAS SD_WE A[23:0] SD_BA[1:0]
CMD
SD4
ROW
COL
SD11
SDDM SD12 D[31:0]
WD1
WD2
WD3
WD4
Figure 13. SDR Write Timing
SD1 SD_CLK SD_CSn, SD_RAS, SD_CAS, SD_WE A[23:0], SD_BA[1:0] SD5 SD3 SD2
CMD
SD4
3/4 MCLK Reference
ROW
COL
tDQS
SDDM SD6 SD_SDR_DQS
(Measured at Output Pin) Board Delay
SD8
SD_DQS[3:2]
(Measured at Input Pin) Board Delay
SD7
Delayed SD_CLK SD9 D[31:0] from Memories
WD1 WD2 WD3 WD4
NOTE: Data driven from memories relative to delayed memory clock.
SD10
Figure 14. SDR Read Timing
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Preliminary Electrical Characteristics
5.7.2
DDR SDRAM AC Timing Characteristics
When the SDRAM controller is configured for DDR SDRAM, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early board design. Table 14. DDR Timing Specifications
Num Characteristic Frequency of Operation DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 Clock Period Pulse Width High Pulse Width Low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] Output Hold Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode) Input Data Skew Relative to DQS (Input Setup) Symbol tDDCK tDDSK tDDCKH tDDCKL tSDCHACV tSDCHACI tCMDVDQ tDQDMV tDQDMI tDVDQ tDIDQ Min 50 12.5 0.45 0.45 -- 2.0 -- 1.5 1.0 -- 0.25 x SD_CLK + 0.5ns 0.5 0.9 0.4 0.25 0.4 Max 80 20 0.55 0.55 0.5 x SD_CLK + 1.0 -- 1.25 -- -- 1 -- -- 1.1 0.6 -- 0.6 Unit Mhz ns SD_CLK SD_CLK ns ns SD_CLK ns ns ns ns ns SD_CLK SD_CLK SD_CLK SD_CLK
5 6 7
Notes
1 2 3 3 4
8 9
DD10 Input Data Hold Relative to DQS.
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH DD12 DQS input read preamble width DD13 DQS input read postamble width DD14 DQS output write preamble width DD15 DQS output write postamble width
1 2 3 4 5
tDQRPRE tDQRPST tDQWPRE tDQWPST
6 7
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same frequency as the internal bus clock. SD_CLK is one SDRAM clock in (ns). Pulse width high plus pulse width low cannot exceed min and max clock period. Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. This specification relates to the required input setup time of today's DDR memories. The device's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation. SD_D[31:24] is relative to SD_DQS3, SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and SD_D[7:0] is relative SD_DQS0. The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats will be valid for each subsequent DQS edge. This specification relates to the required hold time of today's DDR memories. SD_D[31:24] is relative to SD_DQS3, SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and SD_D[7:0] is relative SD_DQS0.
MCF5301x Data Sheet, Rev. 3 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
8
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 9 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid.
SD_CLK VIX VMP VIX SD_CLK VID
Figure 15. SD_CLK and SD_CLK Crossover Timing
DD1 SD_CLK
DD2
DD3
SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
CMD
DD6
ROW
COL
DD7
DM3/DM2 DD8 SD_DQS3/SD_DQS2 DD7 D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DD8
Figure 16. DDR Write Timing
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Preliminary Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
CL=2
CMD CL=2.5 ROW COL DQS Read Preamble
DD10 DD9
SD_DQS3/SD_DQS2 CL = 2
DQS Read Postamble
D[31:24]/D[23:16]
SD_DQS3/SD_DQS2 CL = 2.5
WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 17. DDR Read Timing
5.8
Num G1 G2 G3 G4
1
General Purpose I/O Timing
Table 15. GPIO Timing1
Characteristic FB_CLK High to GPIO Output Valid FB_CLK High to GPIO Output Invalid GPIO Input Valid to FB_CLK High FB_CLK High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
GPIO pins include: IRQn, PWM, UART, and Timer pins.
MCF5301x Data Sheet, Rev. 3 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
FB_CLK
G1
GPIO Outputs
G2
G3
GPIO Inputs
G4
Figure 18. GPIO Timing
5.9
Num R1 R2 R3 R4 R5 R6 R7 R8
1
Reset and Configuration Override Timing
Table 16. Reset and Configuration Override Timing
Characteristic RESET Input valid to FB_CLK High FB_CLK High to RESET Input invalid RESET Input valid Time
1
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns tCYC ns ns tCYC ns tCYC
FB_CLK High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1 R3
RESET
R2
R4
RSTOUT
R4 R8 R5 R6 R7
Configuration Overrides*: (RCON, Override pins])
Figure 19. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5301x Reference Manual for more information.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Preliminary Electrical Characteristics
5.10 5.11
USB On-The-Go SSI Timing Specifications
The MCF53017 device is compliant with industry standard USB 2.0 specification.
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. Table 17. SSI Timing - Master Modes1
Num S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
1 2
Description SSI_MCLK cycle time SSI_MCLK pulse width high / low SSI_BCLK cycle time SSI_BCLK pulse width SSI_BCLK to SSI_FS output valid SSI_BCLK to SSI_FS output invalid SSI_BCLK to SSI_TXD valid SSI_BCLK to SSI_TXD invalid / high impedence SSI_RXD / SSI_FS input setup before SSI_BCLK SSI_RXD / SSI_FS input hold after SSI_BCLK
Symbol tMCLK
Min 8 x tSYS 45% 8 x tSYS 45% -- 0 -- -2 10 0
Max -- 55% -- 55% 15 -- 15 -- -- --
Units ns tMCLK ns tBCLK ns ns ns ns ns ns
Notes
2
tBCLK
3
All timings specified with a capactive load of 25pF. SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not exceed 4 x fSYS.
Table 18. SSI Timing -- Slave Modes1
Num S11 S12 S13 S14 S15 S16 S17 S18
1
Description SSI_BCLK cycle time SSI_BCLK pulse width high / low SSI_FS input setup before SSI_BCLK SSI_FS input hold after SSI_BCLK SSI_BCLK to SSI_TXD / SSI_FS output valid SSI_BCLK to SSI_TXD / SSI_FS output invalid / high impedence SSI_RXD setup before SSI_BCLK SSI_RXD hold after SSI_BCLK
Symbol tBCLK
Min 8 x tSYS 45% 10 2 -- 0 10 2
Max -- 55% -- -- 15 -- -- --
Units ns tBCLK ns ns ns ns ns ns
Notes
All timings specified with a capactive load of 25pF.
MCF5301x Data Sheet, Rev. 3 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
S1
S2
S2
SSI_MCLK (Output)
S3
SSI_BCLK (Output)
S5
S4
S4 S6
SSI_FS (Output)
S9 S10 S7 S7 S8 S8
SSI_FS (Input)
SSI_TXD
S9 S10
SSI_RXD
Figure 20. SSI Timing -- Master Modes
S11
SSI_BCLK (Input)
S15
S12 S12 S16
SSI_FS (Output)
S13
SSI_FS (Input)
S15
S14 S15 S16 S16
SSI_TXD
S17 S18
SSI_RXD
Figure 21. SSI Timing -- Slave Modes
5.12
I2C Input/Output Timing Specifications
Table 19. I2C Input Timing Specifications between SCL and SDA
Num I1 I2 I3 I4 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time Min 2 8 -- 0 Max -- -- 1 -- Units tcyc tcyc ms ns
Table 19 lists specifications for the I2C input timing parameters shown in Figure 22.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Preliminary Electrical Characteristics
Table 19. I2C Input Timing Specifications between SCL and SDA (continued)
Num I5 I6 I7 I8 I9 Characteristic I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min -- 4 0 2 2 Max 1 -- -- -- -- Units ms tcyc ns tcyc tcyc
Table 20 lists specifications for the I2C output timing parameters shown in Figure 22. Table 20. I2C Output Timing Specifications between SCL and SDA
Num I11 I2 1 I3
2
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 10 -- 7 -- 10 2 20 10
Max -- -- -- -- 3 -- -- -- --
Units tcyc tcyc s tcyc ns tcyc tcyc tcyc tcyc
I4 1 I5 3 I6 I7 I8
1 1 1
I9 1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 20. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 20 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 20 and Table 19.
I5 I2 I2C_SCL I1 I2C_SDA I4 I7 I8 I9 I6
I3
Figure 22. I2C Input/Output Timings
MCF5301x Data Sheet, Rev. 3 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
5.13
Fast Ethernet AC Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.
5.13.1
Receive Signal Timing Specifications
Table 21. Receive Signal Timing
MII Mode RMII Mode Unit Min Max -- -- 65% 65% Min 4 2 35% 35% Max -- -- 65% 65% ns ns RXCLK period RXCLK period 5 5 35% 35%
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices.
Num E1 E2 E3 E4
1
Characteristic RXD[n:0], RXDV, RXER to RXCLK setup1 RXCLK to RXD[n:0], RXDV, RXER hold RXCLK pulse width high RXCLK pulse width low
1
In MII mode, n = 3; In RMII mode, n = 1
RXCLK (Input)
E4
E3
E1
E2
RXD[n:0] RXDV, RXER
Valid Data
Figure 23. MII Receive Signal Timing Diagram
5.13.2
Transmit Signal Timing Specifications
Table 22. Transmit Signal Timing
MII Mode RMII Mode Unit Min Max -- 25 65% 65% Min 5 -- 35% 35% Max -- 10 65% 65% ns ns tTXCLK tTXCLK 5 -- 35% 35%
Num E5 E6 E7 E8
1
Characteristic TXCLK to TXD[n:0], TXEN, TXER invalid1 TXCLK to TXD[n:0], TXEN, TXER valid TXCLK pulse width high TXCLK pulse width low
1
In MII mode, n = 3; In RMII mode, n = 1
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Preliminary Electrical Characteristics
TXCLK (Input)
E6
E8
E7 E5
TXD[n:0] TXEN, TXER
Valid Data
Figure 24. MII Transmit Signal Timing Diagram
5.13.3
Num E9
Asynchronous Input Signal Timing Specifications
Table 23. MII Transmit Signal Timing
Characteristic CRS, COL minimum pulse width Min 1.5 Max -- Unit TXCLK period
CRS, COL
E9
Figure 25. MII Async Inputs Timing Diagram
5.13.4
MII Serial Management Timing Specifications
Table 24. MII Serial Management Channel Signal Timing
Characteristic MDC cycle time MDC pulse width MDC to MDIO output valid MDC to MDIO output invalid MDIO input to MDC setup MDIO input to MDC hold Symbol tMDC Min 400 40 -- 25 10 0 Max -- 60 375 -- -- -- Unit ns % tMDC ns ns ns ns
Num E10 E11 E12 E13 E14 E15
MCF5301x Data Sheet, Rev. 3 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
E10 E11
MDC (Output)
E11 E12 E13
MDIO (Output)
Valid Data
E14
E15
MDIO (Input)
Valid Data
Figure 26. MII Serial Management Channel TIming Diagram
5.14
32-Bit Timer Module Timing Specifications
Table 25. Timer Module AC Timing Specifications
Name T1 T2 Characteristic DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width Min 3 1 Max -- -- Unit tCYC tCYC
Table 25 lists timer module AC timings.
5.15
DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many of the transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the MCF5301x Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 26. DSPI Module AC Timing Specifications1
Name DS1 DS2 Characteristic DSPI_SCK Cycle Time DSPI_SCK Duty Cycle Symbol tSCK -- Min 4 x tSYS (tsck / 2) - 2.0 Max -- (tsck / 2) + 2.0 Unit ns ns Notes
2 3
Master Mode DS3 DS4 DS5 DS6 DS7 DS8 DSPI_PCSn to DSPI_SCK delay DSPI_SCK to DSPI_PCSn delay DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold tCSC tASC -- -- -- -- (2 x tSYS) - 1.5 (2 x tSYS) - 3.0 -- -5 9 0 -- -- 5 -- -- -- ns ns ns ns ns ns
4 5
Slave Mode DS9 DSPI_SCK to DSPI_SOUT valid -- -- 4 ns
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Preliminary Electrical Characteristics
Table 26. DSPI Module AC Timing Specifications1 (continued)
Name DS10 DS11 DS12 DS13 DS14
1 2 3 4 5
Characteristic DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven
Symbol -- -- -- -- --
Min 0 2 7 -- --
Max -- -- -- 20 18
Unit ns ns ns ns ns
Notes
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges. When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR]. This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR], DCTARn[CPHA], and DCTARn[PBR]. The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK]. The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS3
DS4
DSPI_PCSn
DS1 DS2
DSPI_SCK (DCTARn[CPOL] = 0)
DS2
DSPI_SCK (DCTARn[CPOL] = 1)
DS7 DS8
DSPI_SIN
First Data DS6
Data
Last Data
DS5 Data Last Data
DSPI_SOUT
First Data
Figure 27. DSPI Classic SPI Timing -- Master Mode
MCF5301x Data Sheet, Rev. 3 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
DSPI_SS
DS1
DSPI_SCK (DCTARn[CPOL] = 0)
DS2
DS2
DSPI_SCK (DCTARn[CPOL] = 1)
DS13 DS10 First Data DS11 DS12 Data Last Data Data DS9 Last Data
DS14
DSPI_SOUT
DSPI_SIN
First Data
Figure 28. DSPI Classic SPI Timing -- Slave Mode
5.16
eSDHC Electrical Specifications
This section describes the electrical information of the eSDHC.
5.16.1
eSDHC Timing
Figure 29 depicts the timing of eSDHC, and Table 29 lists the eSDHC timing characteristics.
SD2 SD5 SD4 SD1
SDHC_CLK
SD3
Output from eSDHC to card SDHC_CMD SDHC_DAT[3:0]
SD6
SD7
SD8
Input from card to eSDHC SDHC_CMD SDHC_DAT[3:0]
Figure 29. eSDHC Timing
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
Preliminary Electrical Characteristics
Table 27. eSDHC Interfacde Timing Specifications
ID Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed) Clock Frequency (MMC Full Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time Clock High Time Clock Rise Time Clock Fall Time fPP1 fPP2 fPP3 fOD4 tWL tWH tTLH tTHL 0 0 0 100 7 7 -- -- 400 25 20 400 -- -- 3 3 kHz MHz MHz kHz ns ns ns ns Parameter Symbols Min Max Unit
eSDHC Output / Card Inputs SDHC_CMD, SDHC_DAT (Reference to SDHC_CLK) SD6 eSDHC Output Delay tOD -5 5 ns
eSDHC Input / Card Outputs SDHC_CMD, SDHC_DAT (Reference to SDHC_CLK) SD7 SD8
1 2
eSDHC Input Setup Time eSDHC Input Hold Time
tISU tIH
4 0
-- --
ns ns
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value from 0 to 25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value from 0 to 20 MHz. 4 In card identification mode, card clock must be 100 kHz - 400 kHz, voltage ranges from 2.7 to 3.6 V.
5.16.2
eSDHC Electrical DC Characterisics
Table 28. MMC/SD Interface Electrical Specifications
Table 28 lists the eSDHC electrical DC characteristics.
Num General 1
Parameter
Design Value
Min
Max
Unit
Condition/Remark
Peak Voltage on All Lines
--
-0.3
VDD + 0.3
V
All Inputs 2 Input Leakage Current -- -10 10 uA
All Outputs 3 Output Leakage Current -- -10 10 uA
Power Supply 4 Supply Voltage (HV card) 3.1 2.7 3.6 V for high voltage cards, must provide this voltage for card initialization for low voltage cards
5
Supply Voltage (LV card)
1.8
1.65
1.95
V
MCF5301x Data Sheet, Rev. 3 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 28. MMC/SD Interface Electrical Specifications (continued)
Num 5 6 Parameter Power Up Time Supply Current Design Value -- -- Min -- 100 Max 250 200 Unit ms mA Condition/Remark
Bus Signal Line Load 7 8 Pull-up Resistance Open Drain Resistance 47 NA 10 NA 100 NA kohm kohm Internal PU For MMC cards only For MMC cards only -- -- VDD - 0.2 -- -- 0.3 V V IOH = -100 A IOL= 2 mA
Open Drain Signal Level 9 10 Output High Voltage Output Low Voltage
Bus Signal Levels 11 12 13 14 Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage -- -- -- -- 0.75 x VDD -- 0.625 x VDD VSS - 0.3 -- 0.125 x VDD VDD + 3 0.25 x VDD V V V V IOH = -100 A @VDD min IOL = 100 A @VDD min
5.17
SIM Electrical Specifications
Each SIM card interface consist of a total of 12 pins (two separate ports of six pins each. Mostly one port with 5 pins is used). The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data, like a standard UART. All six (or five when a bidirectional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between the signals in normal mode. However, there are some in reset and power down sequences.
5.17.1
General Timing Requirements
1/Sfreq
Figure 30 shows the timing of the SIM module, and Table 29 lists the timing parameters.
SIM_CLK
Sfall
Srise
Figure 30. SIM Clock Timing Diagram
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43
Preliminary Electrical Characteristics
Table 29. SIM Timing Specification--High Drive Strength
Num 1 2 3 4
1 2
Description SIM Clock Frequency (SIM_CLK)1 SIM_CLK Rise Time 2 SIM_CLK Fall Time 3 SIM Input Transition Time (RX, SIM_PD)
Symbol Sfreq Srise Sfall Strans
Min 0.01 - - -
Max 5 (Some new cards may reach 10) 20 20 25
Unit MHz ns ns ns
50% duty cycle clock With C = 50pF 3 With C = 50pF
5.17.2
5.17.2.1
* * *
Reset Sequence
Cards with Internal Reset
The reset sequence for this kind of SIM card is as follows (see Figure 31): After powerup, the clock signal is enabled on SIM_CLK (time T0) After 200 clock cycles, RX must be high. The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0.
SIM_VEN
SIM_CLK
SIM_RX 1 2
Response
1 T0 400 clock cycles < 2
< 200 clock cycles < 40,000 clock cycles
Figure 31. Internal-Reset Card Reset Sequence
5.17.2.2
1. 2. 3. 4. 5.
Cards with Active-Low Reset
The sequence of reset for this kind of card is as follows (see Figure 32): After powerup, the clock signal is enabled on SIM_CLK (time T0) After 200 clock cycles, RX must be high. SIM_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those 40,000 clock cycles) SIM_RST is set high (time T1) SIM_RST must remain high for at least 40,000 clock cycles after T1 and a response must be received on RX between 400 and 40,000 clock cycles after T1.
MCF5301x Data Sheet, Rev. 3 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
SIM_VEN
SIM_RST
SIM_CLK
SIM_RX 1 2
Response
3 T0 T1
3
1 400 clock cycles < 400,000 clock cycles < 2 3
< 200 clock cycles < 40,000 clock cycles
Figure 32. Active-Low-Reset Card Reset Sequence
5.17.3
1. 2. 3. 4. 5.
Power Down Sequence
Power down sequence for SIM interface is as follows: SIM_PD port detects the removal of the SIM card SIM_RST goes low SIM_CLK goes low SIM_TX goes low SIM_VEN goes low
Each of these steps is completed in one CKIL period (usually 32 kHz). Power-down may be started in response to a card-removal detection or launched by the processor. Figure 33 and Table 30 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value. Table 30. Timing Requirements for Power Down Sequence
Num 1 2 3 4 Description SIM reset to SIM clock stop SIM reset to SIM TX data low SIM reset to SIM Voltage Enable Low SIM Presence Detect to SIM reset Low Symbol Srst2clk Srst2dat Srst2ven Spd2rst Min 0.9 / fCKIL 1.8 / fCKIL 2.7 / fCKIL 0.9 / fCKIL Max 0.8 1.2 1.8 25 Unit s s s ns
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45
Preliminary Electrical Characteristics
Spd2rst
SIM_PD
SIM_RST Srst2clk
SIM_CLK Srst2dat SIM__TX
Srst2ven SIM_VEN
Figure 33. SmartCard Interface Power-Down AC Timing
5.18
Num 1
1
IIM/Fusebox Electrical Specifications
Table 31. IIM/Fusebox Timing Characteristics
Description Program time for eFuse1 Symbol tprogram Min 125 Max -- Unit s
The program length is defined by the value defined in IIM_FCR[PRG_LENGTH] of the IIM module. The value to program is based on a 32 kHz clock source (4 / 32 kHz = 125 s)
5.19
Voice Codec
The voice codec function is analog-to-digital and digital-to-analog conversion of the voice signal. The following section contains detailed electrical specifications for the analog and digital parts' performance. The voice codec is powered down when not enabled for power consumption.
MCF5301x Data Sheet, Rev. 3 46 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 32 shows the voice codec general specifications. Table 32. Voice Codec General Specifications
Parameter CODEC Input clock CODEC_CLK Condition VCLK[2:0]=0 VCLK[2:0]=1,2 VCLK[2:0]=3 VCLK[2:0]=4 VCLK[2:0]=5 VCLK[2:0]=6 VCLK[2:0]=7 No Load, AVDD (CODEC_REGBYP) = 2.5V Min -- -- -- -- -- -- -- 1.225 Typ 16.8 19.44 20.0 24.0 26.0 28.0 30.0 1.325 Max -- -- -- -- -- -- -- 1.425 Units MHz MHz MHz MHz MHz MHz MHz V
VAG input Voltage
Ref_Codec_p Ref_Codec_n VAG External Cap avoco_ref_codec_p External Cap avoco_ref_codec_n External Cap avoco_vagout_codec External Cap Codec Analog Supply Current (includes Rx and Tx paths) AVDD (CODEC_REGBYP) = 2.5V, operational Power-down mode Codec Digital Supply Current1 Response to input ON/OFF (settling time at turn on)
1
TBD TBD -- -- -- -- -- -- -- --
1.665 0.985 0.1 0.1 0.1 0.1 5 -- -- --
TBD TBD -- -- -- -- 6 5 1 1
V V F F F F mA A mA ms
Operational mode
More accurate estimation will be given after some progress in design.
5.19.1
Voice Codec ADC Specifications
Voice coding function includes a 50 kHz second-order, low-pass anti-aliasing filter, an analog-to-digital converter, digital filters for decimation, band-passing, frequency ripple compensation, and DSP interface logic. The audio input A/D converter converts the incoming signal to 13-bit two's-compliment linear PCM words at an 8 or 8.1 kHz rate. Following the A/D converter, the signal is digitally filtered, low-pass, and selectable high-pass. Table 33 shows the voice coding specifications. Table 33. Voice Codec ADC Specifications1
Parameter Power Supply Rejection Ratio with respect to AVDD (CODEC_REGBYP)2 Peak Input Tx AC Input Impedance Absolute Gain Condition 20Hz to 100kHz, with 100 mVpp noise applied to AVDD, with an external VAG cap Min 50 Typ 60 Max -- Units dB
(+3dBm0)3 on an individual differential VAG-0.34 pin (ADC_P or ADC_M) f=1.02kHz 0dBm0@1.02kHz 100 -1.0
-- -- --
VAG+0.34 -- 1.0
V k dB
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 47
Preliminary Electrical Characteristics
Table 33. Voice Codec ADC Specifications1 (continued)
Parameter Gain vs. Signal Condition Relative to -10dBm0 @1.02kHz +3 to -40dBm0 -40 to -50dBm0 -50 to -55dBm0 1.02kHz tone (linear) +2dBm04 0dBm0 -6dBm0 -10dBm0 -20dBm0 -30dBm0 -40dBm0 -45dBm0 -55dBm0 Psophometric Weighting at the output 57 60 60 55 45 35 25 20 15 -- -- Relative to 0dBm0@1.02kHz 50Hz 60Hz7 200Hz 300 to 3000Hz 3400Hz8 4000Hz 4600Hz Relative to 0dBm0@1.02kHz 50Hz 200Hz 300 to 3000Hz 3400Hz9 4000Hz 4600Hz 1.02kHz @ 0dBm0, 300 to 3kHz D/A = 0 dBm0 @1.02kHz Measured while stimulated w/ 2667Hz @-50dBm0 Two frequencies of amplitudes -4 to -21 dBm0 from the range 300 to 3400Hz -0.5 -0.5 -0.5 -1.0 -- -- -- -- -- -- -- -- -- -- -- -- +0.5 +0.5 +0.5 +0.1 -14 -35 -48 -75 dB dB dB dB dB dB dB dB -8 -0.5 -1.0 -- -- -- -- -- -- -- -- -- -- -- -25 -23 -0.5 +0.5 +0.1 -14 -35 dB dB dB dB dB dB dB 60 64 70 65 55 45 35 30 20 -- -- -- -- -- -- -- -- -- -- -- -72 5 dB dB dB dB dB dB dB dB dB dBm0p %Full Scale Min -0.25 -1.2 -1.3 Typ -- -- -- Max 0.25 1.2 1.3 Units dB dB dB
Total Distortion (noise and harmonic) (300Hz - 20kHz Noise BW in 300Hz - 4kHz measured BW out)
Idle Channel Noise5 Digital Offset6 Frequency Response VCIHPF = logic high
Frequency Response VCIHPF=logic low
Inband Spurious Crosstalk D/A to A/D
Intermodulation Distortion
--
--
-41
dB
MCF5301x Data Sheet, Rev. 3 48 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 33. Voice Codec ADC Specifications1 (continued)
Parameter Filter Group Delay VCIHPF=logic high CODEC_CLK=26MHz (Relative to 1.6kHz) Condition 500Hz < f < 600Hz 600Hz < f < 800Hz 800Hz < f < 1kHz 1kHz < f < 1.6kHz 1.6kHz < f < 2.6kHz 2.6kHz < f < 2.8kHz 2.8kHz < f < 3.0kHz f < 1.6kHz 1.6kHz < f < 2.6kHz 2.6kHz < f < 2.8kHz 2.8kHz < f < 3.0kHz f=1.6kHz f=1.6kHz with 0dBm0 input signal from 4.6 kHz to 8.4 kHz Min -- -- -- -- -- -- -- -40 0 -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 260 155 57 15 95 135 190 0 100 150 200 300 235 -50 Units S S S S S S S S S S S S S dB
Filter Group Delay VCIHPF=logic low CODEC_CLK=26MHz (Relative to 1.6kHz) Filter Absolute Group Delay VCIHPF=logic high Filter Absolute Group Delay VCIHPF=logic low Out of Band input fold-in spurious
1 2
3 4
5 6 7 8 9
All analog signals are referenced to VAG unless otherwise noted. Power Supply Rejection Ratio is for Longjing IC only. Total PSRR from battery to output is obtained by summing the PSRR from Neptune to the one from the Regulator in Seaweed. It is assumed that the regulators in Seaweed will have a minimum PSRR of 45 dB. For A/D differential input (ADC_P - ADC_M) 0dBm0 = 340mVrms. The codec output will not "foldback" or oscillate if overdriven, but clip. The digital word corresponding to +3dBm0 is `0111111111111'b. Therefore if the audio level is set to +3dBm0, any variation in gain could cause large distortion if the digital number exceeds `0111111111111'b. For this reason the maximum recommended signal for low distortion is +3dBm0 - (Absolute Gain Error) = +2dBm0. GSM Spec = -64 0dB. This value is a preliminary target. The final number will be specified after obtaining the production statistical data. Small frequency response deviation from straight line in the 60:200 Hz range is acceptable by spec requirements. Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements. Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 49
Preliminary Electrical Characteristics
Figure 34 and Figure 35 show the filter frequency response for the audio signal for voice coding path. (All filter frequencies increase by 8.1/8.0 if VCLK is selected to generate fSYNC=8.1kHz).
4
+0.5dB @ 3.0kHz
0
+0.1dB @ 3.4kHz
-0.5dB @ 3.0kHz
-5
-1.0dB @ 3.4kHz
-10
-14dB @ 4.0kHz
-15
dB
-20
-25
-30
-35dB @ 4.6kHz
-35 -38 20 30 40 50 70 100 200 300 400 500 700 1000 2000 3000 4000 5000 8000
Hz
Figure 34. Voice Signal Frequency Response Requirements at the ADC Path (VCIHPF=0, LPF Alone Without HPF)
MCF5301x Data Sheet, Rev. 3 50 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
4 +0.5dB @ 300Hz 0 -0.5dB @ 200Hz -0.5dB @ 3.0kHz -1.0dB @ 3.4kHz -8.0dB @ 200Hz +0.1dB @ 3.4kHz +0.5dB @ 3.0kHz
-5
-0.5dB @ 300Hz
-10
-14dB @ 4.0kHz
-15
-23dB @ 60Hz
dB
-20 -25dB @ 50Hz
-25
-30
-35dB @ 4.6kHz
-35 -38 20
30
40
50
70
100
200
300 400 500 700
1000
2000
3000 40005000
8000
Hz
Figure 35. Voice Signal Frequency Response Requirements at the ADC Path (VCIHPF=1, HPF and LPF Together)
5.19.2
Voice Codec DAC Specifications
Voice-decoding function includes frequency ripple compensation, interpolation, digital-to-analog conversion, and anti-imaging filter. The input signal for the voice-decoding function is in linear 16-bit two's compliment PCM words at an 8 kHz or 8.1 kHz rate. Table 34 shows the voice decoding specifications. Table 34. Voice Codec DAC Specifications1
Parameter Output Level Condition +3dbm02 (clipping level) on an individual differential output pin (CODEC_DACP or CODEC_DACN) 10k Load 20Hz to 100kHz with 100 mVrms, noise applied to AVDD (CODEC_REGBYP) 0dBm0@1.02kHz -10dBm0@1.02kHz +3 to -40dBm0 -40 to -50dB -50 to -55dBm0 -0.25 -1.2 -1.3 -- -- -- 0.25 1.2 1.3 dB dB dB Min VAG-0.5 Typ -- Max VAG+0.5 Units V
Output Source Impedance Output Power Supply Rejection Ratio Absolute Gain Gain vs. Signal
-- 50
100 60
-- --
dBa
-1.0
--
1.0
dB
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 51
Preliminary Electrical Characteristics
Table 34. Voice Codec DAC Specifications1 (continued)
Parameter Total Distortion Condition 1.02 kHz tone (linear) +2 dBm0 0 dBm0 -6 dBm0 -10 dBm0 -20 dBm0 -30 dBm0 -40 dBm0 -45 dBm0 -55 dBm0 A weighted to 20kHz 8kHz, 30Hz BW, D/A = zero code TA = 70 C TA = 25 C Relative to 0dBm0@1.02kHz 50Hz 60Hz4 200Hz 300-3000Hz 3400Hz5 4000Hz 4600Hz Relative to 0dBm0@1.02kHz 50Hz 200Hz 300-3000Hz 3400Hz6 4000Hz 4600Hz 1.02kHz @ 0dBm0, 300 to 3kHz -0.5 -0.5 -0.5 -0.8 -- -- -- -- -- -- -- v -- -- -- -- -50 -50 -50 -- -- -- -- -75 -41 dB dB dB dB dB +0.5 +0.5 +0.5 +0.1 -14 -35 -48 dB dB dB dB dB dB dB -- -- -8 -0.5 -0.8 -- -- -- -- -- -- -- -- -- -25 -23 -0.5 +0.5 +0.1 -14 -35 dB dB dB dB dB dB dB -- -- 57 60 60 55 45 35 25 20 15 -- 60 64 70 65 55 45 35 30 20 -78 No spurious -- -- 40 30 mV -- -- -- -- -- -- -- -- -- -73 dB dB dB dB dB dB dB dB dB dBm0 Min Typ Max Units
(4 kHz noise BW in 300 Hz - 20 kHz measured BW out)
Idle Channel Noise3 (At CODEC out) Differential offset Frequency Response VCOHPF = logic high (Min. limit valid for CODEC_CLK=26MHz)
Frequency Response VCOHPF = logic low (Min. limit valid for CODEC_CLK=26MHz)
Inband Spurious
Out-of-Band Spurious 300 to 3400Hz @ 0dBm0 input (Interpolation Image Suppression) 4600 to 7600Hz 7600 to 8400Hz 8400 to 20,000Hz Crosstalk A/D to D/A Intermodulation Distortion A/D = 0dBm0 @1.02kHz Two frequencies. of amplitudes -4 to -21 dBm0 from the range 300 to 3400Hz
MCF5301x Data Sheet, Rev. 3 52 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 34. Voice Codec DAC Specifications1 (continued)
Parameter Filter Group Delay VCOHPF = logic high CODEC_CLK=26 MHz (Relative to 1.6kHz) Condition 500Hz < f < 600Hz 600Hz < f < 800Hz 800Hz < f < 1kHz 1kHz < f < 1.6kHz 1.6kHz < f < 2.6kHz 2.6kHz < f < 2.8kHz 2.8kHz < f < 3.0kHz f < 1.6kHz 1.6kHz < f < 2.6kHz 2.6kHz < f < 2.8kHz 2.8kHz < f < 3.0kHz f=1.6kHz f=1.6kHz Min -- -- -- -- -- -- -- -40 0 -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 300 200 70 30 95 135 190 0 100 160 200 350 320 Units s s s s s s s s s s s s s
Filter Group Delay VCOHPF = logic low CODEC_CLK=26 MHz (Relative to 1.6kHz) Filter Absolute Group Delay VCOHPF = logic high Filter Absolute Group Delay VCOHPF = logic low
1 2 3 4 5 6
All analog signals are referenced to VAG unless otherwise noted. Output is 0dbm0 unless noted. For D/A differential output (CODEC_DACP - CODEC_DACN) 0dBm0 = 500 mVrms. GSM Spec = -64. Small frequency response deviation from straight line in the 60:200 Hz range is acceptable by spec requirements. Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements. Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 53
Preliminary Electrical Characteristics
Figure 36 and Figure 37 show the filter frequency response for the audio signal for voice decoding. The requirements for the decoding path at 3.4 kHz are slightly different from the coding path. (All filter frequencies increase by 8.1/8.0 if VCLK is selected to generate fSYNC = 8.1 kHz).
4 +0.5dB @ 3.0kHz 0 -0.5dB @ 3.0kHz -5 -0.8dB @ 3.4kHz -10 -14dB @ 4.0kHz +0.1dB @ 3.4kHz
-15
dB
-20
-25
-30
-35dB @ 4.6kHz
-35 -38 20 30 40 50 70 100 200 300 400 500 700 1000 2000 300040005000 8000
Hz
Figure 36. Voice Signal Frequency Response Requirements at the DAC Path (VCOHPF=0, LPF Alone Without HPF)
MCF5301x Data Sheet, Rev. 3 54 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
4 +0.5dB @ 300Hz 0 -0.5dB @ 200Hz -0.5dB @ 3.0kHz -0.8dB @ 3.4kHz -8.0dB @ 200Hz +0.1dB @ 3.4kHz +0.5dB @ 3.0kHz
-5
-0.5dB @ 300Hz
-10 -23dB @ 60Hz
-14dB @ 4.0kHz
-15
dB
-20 -25dB @ 50Hz
-25
-30
-35dB @ 4.6kHz
-35 -38 20
30
40
50
70
100
200
300 400 500 700
1000
2000
3000 40005000
8000
Hz
Figure 37. Voice Signal Frequency Response Requirements at the DAC Path (VCOHPF=1, HPF and LPF Together)
5.20
5.20.1
Integrated Amplifiers
Speaker Amplifier
The speaker amplifier boosts the power from the DAC and drives the speaker. It also provides analog volume control to optimize the noise performance of the entire channel. Table 35 shows the specifications for the speaker amplifier. Table 35. Speaker Amplifier Specifications
Parameter Quiescent Current Shutdown Current Input Reference Offset Max Output Power Total Harmonic Distortion (THD) Fin = 1kHz, THD+N = 1%, RL = 4 Gain = 0dB, RL = 4, Fin = 1kHz Gain = 0dB, RL = 4, Fin = 4kHz Integrated Output Noise Full Power, 500mW Half Power, 250mW Full Power, 500mW Half Power, 250mW Conditions Min -- -- -- -- -- -- -- -- -- Typ 800 TBD 2 600 0.050 0.050 0.1 0.1 15 Max -- -- 5 -- -- -- -- -- -- V mV mW % Units A
Gain = 0dB, BW = 20Hz - 20kHz
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 55
Preliminary Electrical Characteristics
Table 35. Speaker Amplifier Specifications (continued)
Parameter Signal to Noise Ratio (SNR) Power Supply Rejection Ratio (PSRR) Conditions Gain = 0dB, VOUT = 1.4VRMS, BW = 20Hz - 20kHz Gain = 0dB, Vripple = 200mVpp f = 217Hz f = 1kHz f = 4kHz Max. Cap Load Drive Output SC Current Gain Error Gain = -45,-21, -6, 0, 4, 6 dB No Sustained Oscillations Min -- -- -- -- -- -- -- Typ 99 60 60 60 300 625 0.5 Max -- -- -- -- -- -- -- pF mA dB Units dB dB
5.20.2
Handset Amplifier
The handset amplifier boosts the power from the DAC and drives the handset. It also provides analog volume control to optimize the noise performance of the entire channel. Table 36 shows the specifications for handset amplifier. Table 36. Handset Amplifier Specifications
Parameter Quiescent Current Shutdown Current Input Reference Offset Max. Output Power Total Harmonic Distortion (THD) Fin = 1kHz, THD + N = 1%, RL = 8 Gain = 0dB, RL = 8, Fin = 1kHz Gain = 0dB, RL = 8, Fin = 4kHz Integrated Output Noise Signal to Noise Ratio (SNR) Power Supply Rejection Ratio (PSRR) Full Power, 250mW Half Power, 125mW Full Power, 250mW Half Power, 125mW Conditions Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Gain = -45, -21, -6, 0, 4, 6 dB -- Typ 800 TBD 2 300 0.050 0.050 0.1 0.050 15 99 60 60 60 300 325 0.5 Max -- -- 5 -- -- -- -- -- -- -- -- -- -- -- -- -- pF mA dB V dB dB mV mW % Units A
Gain = 0dB, BW = 20Hz - 20kHz Gain = 0dB, VOUT = 1.4VRMS , BW = 20Hz - 20kHz Gain = 0dB, Vripple = 200mVpp f = 217Hz f = 1kHz f = 4kHz
Maximum Cap Load Drive Output SC Current Gain Error
No Sustained Oscillations
MCF5301x Data Sheet, Rev. 3 56 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
5.20.3
Headphone Amplifier
The headphone amplifier boosts the power from the DAC and drives the headphone. It also provides analog volume control to optimize the noise performance of the entire channel. Table 37 shows the specifications for the microphone amplifier. Table 37. Headphone Amplifier Specifications
Parameter Quiescent Current Shutdown Current Input Reference Offset Output Power Total Harmonic Distortion (THD) Fin = 1kHz, THD+N = 1%, RL = 16 Gain = 0dB, RL = 16, Full Power, 31.25mW BW = 200Hz - 4kHz Half Power, 16.5mW Gain = 0dB, BW = 20Hz - 20kHz Gain = 0dB, VOUT = 0.7VRMS , BW = 20Hz - 20kHz Gain = 0dB, Vripple = 200mVpp f = 217Hz f = 1kHz f = 4kHz Maximum Cap Load Drive Output SC Current Gain Error Gain = -45, -21, -12, -6, -2, 0 dB No Sustained Oscillations Conditions Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 600 TBD 2 40 0.05 0.05 15 93 60 60 60 300 150 0.5 Max -- -- 5 -- -- -- -- -- -- -- -- -- -- -- pF mA dB V dB dB mV mW % Units A
Integrated Output Noise Signal to Noise Ratio (SNR) Power Supply Rejection Ratio (PSRR)
5.20.4
Microphone Amplifier
The microphone amplifier boosts the signal from the microphone and provides it to the ADC. The gain control present in the microphone amplifier helps in optimizing the noise performance of the entire channel. Table 38 shows the specifications for the microphone amplifier. Table 38. Microphone Amplifier Specifications
Parameter Quiescent Current Shutdown Current Input Reference Offset Conditions Min -- -- -- Typ 500 TBD 2 Max -- -- 5 mV Units A
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 57
Preliminary Electrical Characteristics
Table 38. Microphone Amplifier Specifications (continued)
Parameter Total Harmonic Distortion (THD) Conditions Gain = 0dB, Fin = 1k VOUT = 0.5VRMS VOUT = 0.35VRMS Gain = 20dB, Fin = 1k VOUT = 0.5VRMS VOUT = 0.35VRMS Gain = 0dB, Fin = 4k VOUT = 0.5VRMS VOUT = 0.35VRMS Gain = 20dB, Fin = 4k VOUT = 0.5VRMS VOUT = 0.35VRMS Integrated Output Noise BW = 20Hz - 20kHz Gain = 0dB Gain = 20dB Signal to Noise Ratio (SNR) VOUT = 0.5VRMS, BW = 20Hz - 20kHz VOUT = 0.35VRMS, BW = 20Hz - 20kHz Gain = 0dB, Vripple = 200mVpp Gain = 0dB, Vripple = 100mVpp Gain = 0dB Gain = 20dB Gain = 0dB Gain = 20dB f = 1kHz f = 4kHz f = 1kHz f = 4kHz Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.5 Typ 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 12 40 92.4 81.9 80 80 60 60 50 50 0.5 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 24.0 dB k dB dB dB dB V Units %
THD plus Noise
Power Supply Rejection Ratio
Commom Mode Rejection Ratio
Gain Error Input Impedance
Gain = 0, 6, 9.56, 15.56, 20, 24, 29.56, 39.9 dB Depends on the Gain Setting
5.21
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
JTAG and Boundary Scan Timing
Table 39. JTAG and Boundary Scan Timing
Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT Min DC 4 26 0 4 26 0 0 4 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- Unit fsys/3 tCYC ns ns ns ns ns ns ns ns
MCF5301x Data Sheet, Rev. 3 58 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 39. JTAG and Boundary Scan Timing (continued)
Num J11 J12 J13 J14
1
Characteristics1 TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High
Symbol tTDODV tTDODZ tTRSTAT tTRSTST
Min 0 0 100 10
Max 26 8 -- --
Unit ns ns ns ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2 J3 VIH J3
TCLK (input)
J4
VIL J4
Figure 38. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 39. Boundary Scan (JTAG) Timing
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 59
Preliminary Electrical Characteristics
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 40. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 41. TRST Timing
5.22
Debug AC Timing Specifications
Table 40. Debug AC Timing Specification
Num D0 D1 D2 D3 D41 D5 D6
1
Table 40 lists specifications for the debug AC timing parameters shown in Figure 42.
Characteristic PSTCLK cycle time PSTCLK rising to PSTDDATA valid PSTCLK rising to PSTDDATA invalid DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT assertion time
Min 1.5 -- 1.5 1 4 5 1
Max 1.5 3.0 -- -- -- -- --
Units tSYS ns ns PSTCLK PSTCLK PSTCLK PSTCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK.
MCF5301x Data Sheet, Rev. 3 60 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package Information
D0
PSTCLK
D1 D2
PSTDDATA[7:0]
Figure 42. Real-Time Trace AC Timing
D5 DSCLK
D3
DSI
Current D4
Next
DSO
Past
Current
Figure 43. BDM Serial Port AC Timing
6
Package Information
The latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/coldfire. The following table lists the package case number per device. Use these numbers in the web page keyword search engine to find the latest package outline drawings. Table 41. Package Information
Device MCF53010 MCF53011 208 LQFP MCF53012 MCF53013 MCF53014 MCF53015 256 MAPBGA MCF53016 MCF53017 98ARH98219A TBD Package Type Case Outline Number
7
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5301x Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 61
8
Revision History
Table 42. Revision History
Revision 3 Date 12 Aug 2009 Location -- Initial public revision Changes
Table 42 summarizes revisions to this document.
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Document Number: MCF53017
Rev. 3 8/2009
Preliminary--Subject to Change Without Notice

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